1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a word line driving circuit of a static random access memory (SRAM) of a CMOS type.
2. Description of the Related Art
An SRAM cell has been known and a CMOS inverter has been often used as a word line driving circuit for driving a word line connected to the memory cell.
FIG. 9 shows a part of a conventional SRAM cell.
In FIG. 9, reference numeral 91 is a memory cell provided in a SRAM, D1, /D1: a pair of complementary bit lines connected to the memory cell 91, WL1: a word line connected to the memory cell 91, 92: a word line driving circuit formed of a CMOS inverter connected to the word line WL1, and 93: a row decoder for decoding an input of an row address to control the word line driving circuit 92.
The memory cell 91 comprises a flip-flop circuit having two inverters, which are cross-connected, and a pair of MOS transistors T11 and T12 for a transfer gate. The inverters comprise enhancement type MOS transistors T13 and T14 for driving and high resistance elements R11 and R12 for load. One end of each of the MOS transistors T11 and T12 is connected to each of a pair of complementary storage nodes a1 and b1 of the flip-flop circuit. The other end of each of the MOS transistors T11 and T12 is connected to each of the paired bit lines D1,/D1, and a gate is connected to the word line WL1 in common.
The MOS transistors T11 and T12 for a transfer gate are turned on or off in accordance with a logic level of the word line WL, respectively, in order to control data transfer among the storage node a1 of the flip-flop circuit, the bit line D1, the storage node b1, and the bit line /D1.
The CMOS inverter 92 for word line driving comprises a PMOS transistor T15 in which a source and a substrate region are connected to a power supply voltage (VDD) node, and an NMOS transistor T16 in which a source and a substrate region are connected to a ground voltage (VSS) node. Gates of both transistors T15 and T16 are mutually connected to each other, and serve as an input node, and drains of both transistors T15 and T16 are mutually connected to each other, and serve as an output node.
FIG. 10 shows an example of the cross sectional structure of both transistors T15 and T16 of the CMOS inverter 92.
In the figure, reference numeral 100 is a semiconductor substrate, 101: an N.sup.- type N well (substrate region of PMOS transistor T15), 102: an N.sup.+ type electrode region of the N well 101, 103a, 103b: P.sup.+ type impurity regions (source and drain of PMOS transistor T15), 104: a P.sup.+ type electrode region of a P well (substrate region of NMOS transistor T16), 106a, 106b: N.sup.+ type impurity regions (source and drain of NMOS transistor T16), 107: an insulation gate film, 108: a gate electrode of PMOS transistor T15, and 109: a gate electrode of NMOS transistor T16.
FIG. 11 is a circuit diagram showing an example of a buffer circuit 110 for writing data to the bit lines D1 and /D1.
FIG. 12 shows an example of a waveform of each node in a writing operation to the memory cell 91 of FIG. 9.
It is assumed that the pair of storage nodes a1 and b1 of the flip-flop circuit of the memory cell 91 are set to an "L" level (VSS)/"H" level (VDD), respectively, in the initial state. In this case, a writing enable signal /WE to be inputted to the buffer circuit 110 is set to "L" level, and a writing data input Din is set to "H" level. In this state, the level of the input signal of the word line driving circuit 92 is changed from "H" to "L." Thereby, if the word line WL1 is in "H" level and the MOS transistors T11 and T12 for transfer gate is turned on, the first storage node b1 is discharged to VSS level, and the second storage node a1 is charged to the level of VDD-Vt11 (Vt11: threshold voltage of MOS transistor T11). In other words, "H" level data is written to the second storage node a1.
Moreover, the second storage node a1 is charged from the VDD node through a high resistor R11, and boosted to a VDD level in a routine state. However, such charging is performed by the high resistor R11 and a time constant of electrostatic capacity of the second storage node a1, and several ms to several tens ms are normally needed. Due to this, such charging is little helpful to the write operation.
Then, writing is ended, the word line driving circuit 92 is in a non-driving state, the word line WL1 is in VSS level, and the MOS transistors T11 and T12 are turned off. Thereafter, data is stored in the memory cell by electric charge Qa1=Ca1.multidot.Va1=Ca1.multidot.VDD-Ca1.multidot.Vt11, which is stored by voltage Va1 of the second storage node a1 and electrostatic capacity Ca1 of the second storage node a1.
By the way, in a case where radioactive rays, particularly .alpha. ray, emitted from radioactive material contained in the material constituting an SRAM package and SRAM is inputted to a semiconductor substrate, an electron is generated in the substrate. If the electron reaches an "H" level data storage node (second storage node a1 of this example), there is generated the so-called soft error in which the electron recombines with a positive electric charge whereby the electric charge Qa1 is lost and storage data of the memory cell 91 cannot be stored.
In order to reduce the generation of the soft error, the electric charge Qa1 stored in the second storage node a1 of the memory cell 91 may become extremely large. As a main electrostatic capacity Ca1 of the storage node a1, there are junction capacitance between the substrate and diffusion layers of the MOS transistor T11 and the MOS transistor T13, and a capacitance between the gate and the channel of the MOS transistor T14. The electrostatic capacity Ca1 may be increased to increase the electric charge Qa1.
However, in recent years, the memory cell has been miniaturized and the transistor has been small-sized in accordance with the highly integrated SRAM whose capacity is enlarged. As a result, in the present circumstances, electrostatic capacity of the storage nodes a1 and b1 has become smaller and smaller.
Moreover, Va1 can be increased to increase the electric charge Qa1. However, for the reason of low power consumption of SRAM, a gate breakdown voltage is decreased since a thickness of a gate oxide film is reduced in accordance with the miniaturization of the transistor. As a result, VDD tends to be lowered. Due to this, the voltage of "H" level data storage node is also lowered. Particularly, the voltage of "H" level data storage node is reduced to VDD--VTH11 (VTH11: threshold voltages of MOS transistor T11) when the writing operation is ended.
Due to this, in the highly integrated SRAM whose capacity is enlarged, the soft error generation rate is increased, and particularly, the soft error is remarkably generated in the memory cell just after the writing operation is ended.
In order to solve the above problem, as shown in FIG. 13, it is considered that a word line boosting circuit 131, which is used in DRAM, and a word line driving circuit 132 using an output of the word line boosting circuit are used.
FIG. 14 shows an example of an operation waveform of the circuit of FIG. 13.
In the word line boosting circuit 131 of FIG. 13, capacitor C having a high value is charged to VDD by a precharge circuit 133, and after a row decoder output /WL has been established (a low level), a node SV is transited from 0 V to VDD level. Whereby, a voltage, which is higher than VDD, is generated at a node WLV. Moreover, due to the rise of the voltage of the node WLV, a node G to which a gate of an NMOS transistor TA for word line driving of the word line driving circuit 132 is increased to the level, which is higher than VDD, by a capacity combination between the gate of the transistor TA and the channel. Then, the boosting level of the node G is maintained by an NMOS transistor TB, so that a voltage, which is higher than VDD, is outputted to the word line WL.
As mentioned above, the "H" level voltage, which is higher than VDD, is outputted to the word line WL, thereby making it possible to compensate for voltage drop corresponding to the threshold of the transfer gate for transferring data between the bit line and the data strange node of the memory cell.
Whereby, the "H" level voltage of the "H" level data storage node is increased when "H" level data writing is ended, and the electric charge to be stored in the storage node is increased by the value corresponding to the increased voltage. As a result, stability of storage data of the memory cell is increased, and the soft error generation rate is reduced.
As mentioned above, increase in the word line voltage can be considered as measures against the soft error generated just after the writing is ended. However, in this case, the boosting circuit 131 is needed to increase the word line voltage to be more than the power supply voltage, and the number of wirings of the boosting circuit 131 is increased. Due to this, there is generated a problem in that the manufacturing cost is increased.
Moreover, there is a limitation in the driving capability of a driver circuit (not shown) for driving the node SV, and the capacity value of capacitor C cannot be unnecessarily increased. Therefore, since power, which the boosting circuit output node WLV can supply, is not so large, it is difficult to drive the word line WL having a high wiring load by the above-mentioned circuit system.
Furthermore, in the boosting circuit 131 of FIG. 13, the input of the node SV must be controlled to be synchronized with an output /WL of a row decoder 134 in order to precharge capacitor C. Due to this, the above-mentioned system cannot be realized by SRAM having no synch signal.
As mentioned above, in the conventional SRAM there was the problem of difficulty in reducing the soft error generation rate caused by the incidence of the radioactive rays just after the writing to the storage node of the SRAM cell.